In current integrated circuit (IC) design systems and processes, IO (input/output) cell design is dictated by the type of package in which the IO cell will be used. There are two main package types, wirebond (WB) and controlled collapse chip connection (C4, also referred to as flip-chip). Each package type, wirebond and C4, has different requirements on the IO cell design and thus conventionally require at least two separate libraries for IC design.
In addition to having different requirements from C4, wirebond is further complicated by the fact that there are at least three unique design techniques that place particular requirements on the IO cell, i.e., core limited, IO limited, and inline. In practice, unique IO cells are designed for each respective design technique. For example, in IO limited designs, the IO cells are tall and narrow rectangles having a length greater than a width (the width being the edge of the IO cell that is parallel to the nearest edge of the die). On the other hand, in core limited designs, the IO cells are short and wide rectangles having a width greater than a length.
As a result, an IO cell that is defined for one of the design techniques (e.g., core limited) is not used with another design technique (e.g., IO limited). Similarly, an IO cell that is defined for any one of the wirebond techniques in not used with a C4 package, and vice versa. Designing different IO cells for the different die and package architectures (e.g., C4, core limited, IO limited, and inline) takes time and resources, and thus introduces inefficiency to the application specific integrated circuit (ASIC) and/or Foundry design process.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.